REACTOR, 320A 3-Ply Face Mask 2 or 4 ranks per

2 or 4 ranks per DIMM • Open with adaptive idle page close timer or closed page policy • Per channel memory test and initialization engine can initialize DRAM to all logical zeros with valid ECC (with or without data scrambler) or a predefined test pattern • Minimum memory configuration: independent channel support with 1 DIMM populated • Integrated dual SMBus master controllers • Command launch modes of 1n/2n • RAS Support (including and not limited to): — Rank Level Sparing and Device Tagging — Demand and Patrol Scrubbing — DRAM Single Device Data Correction (SDDC) for any single x4 or x8 DRAM device failure

• SoC designs can use either SMBus or NC-SI for connectivity to the BMC

single event burnout (SEB)

AOD:8T0-035-223-AQ

Windows XP

REACTOR, 320A 3-Ply Face Mask 2 or 4 ranks perREACTOR, 320A